This invention relates generally to simultaneous double side grinding of semiconductor wafers and more particularly to double side grinding apparatus and methods for improved wafer nanotopology.
Semiconductor wafers are commonly used in the production of integrated circuit chips on which circuitry is printed. The circuitry is first printed in miniaturized form onto surfaces of the wafers, then the wafers are broken into circuit chips. But this smaller circuitry requires that wafer surfaces be extremely flat and parallel to ensure that the circuitry can be properly printed over the entire surface of the wafer. To accomplish this, a grinding process is commonly used to improve certain features of the wafers (e.g., flatness and parallelism) after they are cut from an ingot.
Simultaneous double side grinding operates on both sides of the wafer at the same time and produces wafers with highly planarized surfaces. It is therefore a desirable grinding process. Double side grinders that can be used to accomplish this include those manufactured by Koyo Machine Industries Co., Ltd. These grinders use a wafer-clamping device to hold the semiconductor wafer during grinding. The clamping device typically comprises a pair of hydrostatic pads and a pair of grinding wheels. The pads and wheels are oriented in opposed relation to hold the wafer therebetween in a vertical orientation. The hydrostatic pads beneficially produce a fluid barrier between the respective pad and wafer surface for holding the wafer without the rigid pads physically contacting the wafer during grinding. This reduces damage to the wafer that may be caused by physical clamping and allows the wafer to move (rotate) tangentially relative to the pad surfaces with less friction. While this grinding process significantly improves flatness and parallelism of the ground wafer surfaces, it can also cause degradation of the topology of the wafer surfaces.
In order to identify and address the topology degradation concerns, device and semiconductor material manufacturers consider the nanotopology (NT) of the wafer surfaces. Nanotopology has been defined as the deviation of a wafer surface within a spatial wavelength of about 0.2 mm to about 20 mm. This spatial wavelength corresponds very closely to surface features on the nanometer scale for processed semiconductor wafers. The foregoing definition has been proposed by Semiconductor Equipment and Materials International (SEMI), a global trade association for the semiconductor industry (SEMI document 3089). Nanotopology measures the elevational deviations of one surface of the wafer and does not consider thickness variations of the wafer, as with traditional flatness measurements. Several metrology methods have been developed to detect and record these kinds of surface variations. For instance, the measurement deviation of reflected light from incidence light allows detection of very small surface variations. These methods are used to measure peak to valley (PV) variations within the wavelength.
Double sided grinding is one process which governs the nanotopology (NT) of finished wafers. NT defects like C-Marks and B-Rings take form during grinding process and may lead to substantial yield losses. After double side grinding, the wafer undergoes various downstream processes like edge polishing, double sided polishing, and final polishing as well as measurements for flatness and edge defects before the NT is checked by a nanomapper. In the current practice, the wafer surface is measured immediately after double sided polishing. Thus, there is a delay in determining the NT. Moreover, the wafer is not measured until the cassette of wafers is machined. If suboptimal settings of the grinder cause an NT defect, then, it is likely that all the wafers in the cassette will have this defect leading to larger yield loss. In addition to this, the operator has to wait to get the feedback from the measurements after each cassette which leads to a considerable amount of down-time. If the next cassette is ground without a feedback there is a risk of more yield loss in the next cassette due to improper grinder settings. Also, in the current system only one wafer from each lot is measured. Therefore, there is a need for a reliable prediction of post-polishing NT defects during grinding.
A typical wafer-clamping device 1′ of a double side grinder of the prior art is schematically shown in FIGS. 1 and 2. Grinding wheels 9′ and hydrostatic pads 11′ hold the wafer W independently of one another. They respectively define clamping planes 71′ and 73′. A clamping pressure of the grinding wheels 9′ on the wafer W is centered at a rotational axis 67′ of the wheels, while a clamping pressure of the hydrostatic pads 11′ on the wafer is centered near a center WC of the wafer. As long as clamping planes 71′ and 73′ are held coincident during grinding (FIG. 1), the wafer remains in plane (i.e., does not bend) and is uniformly ground by wheels 9′. A general discussion regarding alignment of clamping planes may be found in U.S. Pat. No. 6,652,358. However, if the two planes 71′ and 73′ become misaligned, the clamping pressures of the grinding wheels 9′ and hydrostatic pads 11′ produce a bending moment, or hydrostatic clamping moment, in the wafer W that causes the wafer to bend sharply generally adjacent peripheral edges 41′ of the grinding wheel openings 39′ (FIG. 2). This produces regions of high localized stress in the wafer W.
Misalignment of clamping planes 71′ and 73′ is common during double side grinding operation and is generally caused by movement of the grinding wheels 9′ relative to the hydrostatic pads 11′ (FIG. 2). Possible modes of misalignment are schematically illustrated in FIGS. 2 and 3. These include a combination of three distinct modes. In the first mode there is a lateral shift S of the grinding wheels 9′ relative to the hydrostatic pads 11′ in translation along an axis of rotation 67′ of the grinding wheels (FIG. 2). A second mode is characterized by a vertical tilt VT of the wheels 9′ about a horizontal axis X through the center of the respective grinding wheel (FIGS. 2 and 3). FIG. 2 illustrates a combination of the first mode and second mode. In a third mode there is a horizontal tilt HT of the wheels 9′ about a vertical axis Y through the center of the respective grinding wheel (FIG. 3). These modes are greatly exaggerated in the drawings to illustrate the concept; actual misalignment may be relatively small. In addition, each of the wheels 9′ is capable of moving independently of the other so that horizontal tilt HT of the left wheel can be different from that of the right wheel, and the same is true for the vertical tilts VT of the two wheels.
The magnitude of hydrostatic clamping moments caused by misalignment of clamping planes 71′ and 73′ is related to the design of the hydrostatic pads 11′. For example, higher moments are generally caused by pads 11′ that clamp a larger area of the wafer W (e.g., pads that have a large working surface area), by pads in which a center of pad clamping is located a relatively large distance apart from the grinding wheel rotational axis 67′, by pads that exert a high hydrostatic pad clamping force on the wafer (i.e., hold the wafer very rigidly), or by pads that exhibit a combination of these features.
In clamping device 1′ using prior art pads 11′ (an example of one prior art pad is shown in FIG. 4), the bending moment in wafer W is relatively large when clamping planes 71′ and 73′ misalign because the wafer is clamped very tightly and rigidly by the pads 11′, including near peripheral edges 41′ of grinding wheel opening 39′. The wafer cannot adjust to movement of grinding wheels 9′ and the wafer bends sharply near opening edges 41′ (FIG. 2). The wafers W are not uniformly ground and they develop undesirable nanotopology features that cannot be removed by subsequent processing (e.g., polishing). Misalignment of clamping planes 71′ and 73′ can also cause the grinding wheels 9′ to wear unevenly, which can further contribute to development of undesirable nanotopology features on the ground wafer W.
FIGS. 5A and 5B illustrate undesirable nanotopology features that can form on surfaces of a ground wafer W when clamping planes 71′ and 73′ misalign and the wafer bends during the grinding operation. The features include center-marks (C-marks) 77′ and B-rings 79′ (FIG. 5A). The center-marks (C-marks) 77′ are generally caused by a combination of lateral shift S and vertical tilt VT of the grinding wheels 9′, while the B-rings 79′ are generally caused by a combination of lateral shift S and horizontal tilt HT of the wheels. As shown in FIG. 5B, both features 77′ and 79′ have relatively large peak to valley variations associated with them. They are therefore indicative of poor wafer nanotopology and can significantly affect ability to print miniaturized circuitry on wafer surfaces.
Misalignment of hydrostatic pad and grinding wheel clamping planes 71′ and 73′ causing nanotopology degradation can be corrected by regularly aligning the clamping planes. But the dynamics of the grinding operation as well as the effects of differential wear on the grinding wheels 9′ cause the planes to diverge from alignment after a relatively small number of operations. Alignment steps, which are highly time consuming, may be required so often as to make it a commercially impractical way of controlling operation of the grinder.
Further, there is usually some lag between the time that undesirable nanotopology features are introduced into a wafer by a double side grinder and the time they are discovered. This is because wafer nanotopology measurements are normally not taken upon removal of the wafer from the grinder. Instead, wafer nanotopology is usually measured after the ground wafer has been polished in a polishing apparatus. Undesirable nanotopology features introduced into the wafer by the double side grinder can be identified in the post-polishing nanotopology measurement. However, negative feedback from a double side grinder problem (e.g., slight misalignment of the grinding wheels and hydrostatic pads) is not available for some time after the problem arises. This may increase the yield loss because the grinder can process a number of additional wafers, introducing nanotopology defects to each one, before the problem is recognized and corrected. Similarly, positive feedback confirming desired operation of the double side grinder (e.g., successful realignment of the grinding wheels and hydrostatic pads) is also not readily available.
Accordingly, there is a need for a hydrostatic pad usable in a wafer-clamping device of a double side grinder capable of effectively holding semi-conductor wafers for processing but still forgiving to movement of grinding wheels so that degradation of wafer surface nanotopology is minimized upon repeated grinder operation. There is also a need for a double side grinding systems that provides nanotopology feedback in less time, allowing adjustments that can be made to improve nanotopology to be recognized and implemented with less lag time for improved quality control and/or wafer yield.